1. Field of the Invention
This invention relates to a vertical semiconductor device used as a power semiconductor device. More particularly, it relates to MOS device having improved breakdown characteristics.
2. Description of the Related Art
Double diffusion type MOS transistors (hereinafter referred to merely as "DMOS") have been proposed in the past as power semiconductor devices.
An n-channel type DMOS device, for example, has a basic structure such as shown in FIG. 13. FIG. 13(a) is a schematic plane view of principal portions of the device and FIG. 13(b) is a sectional view taken along a line 13(b)--13(b) in FIG. 13(a). Like reference numerals are used to identify like constituent members in these drawings.
The DMOS device uses the structure shown in FIG. 13(b) as a unit cell, and is a device which controls a current flowing through a drain terminal D to a source terminal S disposed on both sides of a chip by a potential applied to a gate terminal G. When a potential exceeding a threshold value is applied to a gate electrode 27 relative to a source electrode 29, a surface of a p base layer 23 (channel) below the gate electrode 27 undergoes inversion, and becomes conductive with the drain side by the source electrode 29 through an n.sup.+ source layer 25 and the channel. When the device is turned OFF, a pn junction formed by the p base layer 23 and an n.sup.- drain layer 22 enters a reverse bias state and possesses a withstand voltage which is determined by the thickness and an impurity concentration of the n.sup.- drain layer 22 as a drift region.
A parasitic npn bipolar transistor exists in this DMOS transistor. An electrical equivalent circuit corresponding to FIG. 13(b) is shown in FIG. 14, where R.sub.D is a diffusion resistance inside the p base layer 23 immediately below the n.sup.+ source layer 25, C.sub.1 is a junction capacitance between the n.sup.- drain layer 22 and the p base layer 23, C.sub.2 is a parasitic capacitance between the gate electrode 27 and the n.sup.- drain layer 22, and C.sub.3 is a parasitic capacitance between the gate electrode 27 and the p base layer 23. In other words, the structure constitutes a parasitic npn transistor having the n.sup.+ source layer 25 as its emitter, the p base layer as its base and the n drain layers 21, 22 as its collector.
When a voltage pulse such as a noise signal is applied across the drain electrode 30 and the source electrode 29, the noise current I.sub.B flows into the p base layer 23 through the junction capacitance C.sub.1 between the n.sup.- drain layer 22 and the p base layer 23, the parasitic capacitance C.sub.2 between the gate electrode 27 and the n.sup.- drain layer 22 and the parasitic capacitance C.sub.3 between the gate electrode 27 and the p base layer 23, and reaches a source contact window region ZZ1 while flowing through a portion immediately below the n.sup.+ source layer 25. In this instance, a potential of a vicinity portion ZZ2 of the p base layer 23 and the n.sup.- drain layer 22 becomes higher by a potential V.sub.B expressed by the following equation (1) due to the diffusion resistance R.sub.D inside the p base layer 23: EQU V.sub.B =I.sub.B .times.R.sub.D ( 1)
When this V.sub.B becomes greater than a forward voltage of the pn junction formed by the n.sup.+ source layer 25 and the p base layer 23, the noise current I.sub.B flowing into the p base layer 23 at the vicinity portion ZZ2 of the p base layer and the n.sup.- drain layer flows as such into the n.sup.+ source layer 25 and becomes a base current of a parasitic transistor. Then, this parasitic transistor enters the ON state. In an insulated gate bipolar transistor (IGBT), the operation of the parasitic transistor results in latchup of an internal thyristor.
When a current flows through the parasitic transistor, the temperature of this parasitic transistor rises. In a bipolar transistor, the temperature rise of the device itself reduces its resistance value, so that positive feedback operates in a direction which increases the current. Therefore, currents flowing through other portions of the chip concentrate on one position of the activated parasitic transistor. In other words, a so-called "hot spot" occurs and eventually, the semiconductor device is destroyed. Normally, the device is constituted by the use of a plurality of unit cells shown in FIG. 13(b) and in this case, the operation of the parasitic transistor occurs locally in most cases. In such cases, noise energy concentrates on such a local portion and destroys the device without waiting for positive feedback by heat. To overcome the limitations resulting from such destruction, the operation of this parasitic transistor must be suppressed.
In a prior art insulated gate bipolar transistor (IGBT), a structure equipped with independent extraction layers shown in FIG. 15(a), for example, has been proposed in order to improve latchup resistance at the time of turn-ON of the gate (KOKAI (Japanese Unexamined Patent Publication) No. 63-164473).
Generally, vertical MOS gate device consists of a plurality of unit cells as described above, and the structure shown in FIG. 15(a) can be expressed by an equivalent circuit diagram shown in FIG. 15(b). This circuit arrangement suppresses the rise of the base potential of the parasitic transistor by branching a part of the current flowing through each unit cell to the extraction layer. However, since the parasitic transistor in each unit cell is mutually independent of other such parasitic transistors, there remains the problem that when the parasitic operation occurs, this operation becomes a local operation as described above and the device undergoes destruction even when the amount of energy involved is small.